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D a t a S h e e t , Rev. 1.04, J a n . 2 0 0 4
HYS72D16000GR-[7/8]-A HYS72D32001GR-[7/8]-A
Registered DDR SDRAM-Modules DDR SDRAM
Memory Products
Never
stop
thinking.
Edition 2004-01 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2004. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
D a t a S h e e t , Rev. 1.04, J a n . 2 0 0 4
HYS72D16000GR-[7/8]-A HYS72D32001GR-[7/8]-A
Registered DDR SDRAM-Modules DDR SDRAM
Memory Products
Never
stop
thinking.
HYS72D16000GR-[7/8]-A HYS72D32001GR-[7/8]-A Revision History: Previous Version: Page Rev. 1.04 16 Editorial and table-layout changes Rev. 1.04 Rev. 1.03 2004-01 2003-10
Subjects (major changes since last revision)
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HYS72D[16000/32001]GR-[7/8]-A Registered DDR SDRAM Modules
Table of Contents 1 1.1 1.2 2 3 3.1 3.2 3.3 4 5 6 Page
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 17 17
SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Application Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Data Sheet
5
Rev. 1.04, 2004-01
HYS72D[16000/32001]GR-[7/8]-A Registered DDR SDRAM Modules
Overview
1
1.1
* * * * * * * * * *
Overview
Features
* *
184-pin Registered 8 Byte Dual-In-Line DDR SDRAM Module for PC and Server main memory applications One bank 16M x 72 and 32M x 72 organization JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) with a single +2.5 V ( 0.2 V) power supply Built with 128 Mbit DDR SDRAMs in 66-Lead TSOPII package Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) Auto Refresh (CBR) and Self Refresh All inputs and outputs SSTL_2 compatible Re-drive for all input signals using register and PLL devices. Serial Presence Detect with E2PROM JEDEC standard MO-206 form factor: 133.35 mm (nom.) x 43.18 mm (nom.) x 4.00 mm (max.) (6,80 mm max. with stacked components) JEDEC standard reference layout: Raw Cards A, B and C Gold plated contacts
Table 1
Performance -8/-7 -7 Component Module @CL2.5 @CL2 DDR266A PC2100-2033 -8 DDR200 PC1600-2022 125 100 Unit -- -- MHz MHz
Part Number Speed Code Speed Grade max. Clock Frequency
fCK2.5 fCK2
143 133
1.2
Description
The HYS 72Dxx0x0GR are industry standard 184-pin 8 byte Dual in-line Memory Modules (DIMMs) organized as 16M x 72 (128 MB) and 32M x 72 (256 MB). The memory array is designed with Double Data Rate Synchronous DRAMs for ECC applications. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.
Data Sheet
6
Rev. 1.04, 2004-01 10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A Registered DDR SDRAM Modules
Overview Table 2 Type PC2100 (CL=2) HYS72D16000GR-7-A HYS72D32001GR-7-A PC1600 (CL=2) HYS72D16000GR-8-A HYS72D32001GR-8-A PC1600R-20220-A1 PC1600R-20220-B1 one bank 128 MB Reg. DIMM 128 Mbit (x8) one bank 256 MB Reg. DIMM 128 Mbit (x4) PC2100R-20330-A1 PC2100R-20330-B1 one bank 128 MB Reg. DIMM 128 Mbit (x8) one bank 256 MB Reg. DIMM 128 Mbit (x4) Ordering Information Compliance Code Description SDRAM Technology
Note: All part numbers end with a place code (not shown), designating the silicon-die revision. Reference information available on request. Example: HYS72D16000GR-8-A, indicating Rev. A die are used for SDRAM components The Compliance Code is printed on the module labels and describes the speed sort for example "PC2100R", the latencies (for example "20330" means CAS latency = 2, tRCD latency = 3 and tRP latency = 3 ) and the Raw Card used for this module.
Data Sheet
7
Rev. 1.04, 2004-01 10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A Registered DDR SDRAM Modules
Pin Configuration
2
Table 3 Symbol A0 - A11 BA0, BA1
Pin Configuration
Pin Definitions and Functions Type Input Input Input/Output Input/Output Input Input Input Input Input/Output Input Input Input/Output Input Supply Supply Supply Output Supply Supply Input Output Input Input Input Input Function Address Inputs Rank Selects Data Input/Output Check Bits (x72 organization only) Row Address Strobe Column Address Strobe Read/Write Input Clock Enable SDRAM low data strobes Differential Clock Input SDRAM low data mask high data strobes Chip Selects Power (+2.5 V) Ground I/O Driver power supply
DQ0 - DQ63 CB0 - CB7 RAS CAS WE CKE0, CKE1 DQS0 - DQS8 CK0, CK0 DM0 - DM8 DQS9 - DQS17 CS0, CS1
VDD VSS VDDQ VDDID VDDSPD VREF
SCL SDA SA0 - SA2 NC DU RESET
VDD Indentification flag
EEPROM power supply I/O reference supply Serial bus clock Serial bus data line slave address select no connect don't use Reset pin (forces register inputs low) *)
*) for detailed description of the Power Up and Power Management on DDR Registered DIMMs see the Application Note at the end of this datasheet
Table 4 Density
Address Format Organization Memory Ranks SDRAMs # of SDRAMs # of row/rank/ columns bits 12/2/10 12/2/11 Refresh Period Interval
128 MB 256 MB
16M x 72 32M x 72
1 1
16M x 8 32M x 4
9 18
4K 4K
64 ms 64 ms
15.6 s 15.6 s
Data Sheet
8
Rev. 1.04, 2004-01 10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A Registered DDR SDRAM Modules
Pin Configuration Table 5 PIN# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Pin Configuration Symbol PIN# 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Symbol A0 CB2 PIN# 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 Symbol DQ4 DQ5 PIN# 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 Symbol A10 CB6
VREF
DQ0
VSS
DQ1 DQS0 DQ2
VSS
CB3 BA1 KEY DQ32
VDDQ
DM0/DQS9 DQ6 DQ7
VDDQ
CB7 KEY
VSS
DQ36 DQ37
VDD
DQ3 NC RESET
VSS
NC NC NC
VDDQ
DQ33 DQS4 DQ34
VDD
DM4/DQS13 DQ38 DQ39
VSS
DQ8 DQ9 DQS1
VDDQ
DQ12 DQ13 DM1/DQS10
VSS
BA0 DQ35 DQ40
VSS
DQ44 RAS DQ45
VDDQ
DU DU
VDD
DQ14 DQ15 CKE1
VDDQ
WE DQ41 CAS
VDDQ
CS0 CS1 DM5/DQS14
VSS
DQ10 DQ11 CKE0
VDDQ
NC DQ20 NC/A12
A12 is used for 256 Mbit and 512 Mbit based modules only
VSS
DQS5 DQ42
VSS
DQ46
VDDQ
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
DQ16 DQ17 DQS2
69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
DQ43
116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 9
VSS
DQ21 A11 DM2/DQS11
162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177
DQ47 NC
VDD
NC DQ48 DQ49
VDDQ
DQ52 DQ53 NC
VSS
A9 DQ18 A7
VDD
DQ22 A8 DQ23
VSS
DU DU
VDD
DM6/DQS15 DQ54 DQ55
VDDQ
DQ19 A5 DQ24
VDDQ
DQS6 DQ50 DQ51
VSS
A6 DQ28 DQ29
VDDQ
NC DQ60 DQ61
VSS
DQ25 DQS3 A4
VSS VDDID
DQ56 DQ57
VDDQ
DM3/DQS12 A3 DQ30
VSS
DM7/DQS16 Rev. 1.04, 2004-01 10282003-ROLI-0GQ8
VDD
Data Sheet
HYS72D[16000/32001]GR-[7/8]-A Registered DDR SDRAM Modules
Pin Configuration Table 5 PIN# 39 40 41 42 43 44 45 46 47 Pin Configuration (cont'd) Symbol DQ26 DQ27 A2 PIN# 85 86 87 88 89 90 91 92 93 Symbol PIN# 132 133 134 135 136 137 138 139 140 Symbol PIN# 178 179 180 181 182 183 184 185 - Symbol DQ62 DQ63
VDD
DQS7 DQ58 DQ59
VSS
DQ31 CB4 CB5
VDDQ
SA0 SA1 SA2
VSS
A1 CB0 CB1
VSS
NC SDA SCL
VDDQ
CK0 CK0
VDD
DQS8
VSS
DM8/DQS17
VDDSPD VSS
-
VSS
Data Sheet
10
Rev. 1.04, 2004-01 10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A Registered DDR SDRAM Modules
Pin Configuration
RS0 DQS0 DM0/DQS9
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D0 DQS
DQS4 DM4/DQS13
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D4 DQS
DQS1 DM1/DQS10
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS D1
DQS5 DM5/DQS14
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS D5
DQS2 DM2/DQS11
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D2 DQS
DQS6 DM6/DQS15
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D6 DQS
DQS3 DM3/DQS12
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D3 DQS
DQS7 DM7/DQS16
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS D7
DQS8 DM8/DQS17
VDDSPD Serial PD CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D8 DQS SDA SCL A0 A1 A2 VDD, V DDQ VREF V SS V DDID
EEPROM D0 - D8 D0 - D8 D0 - D8 D0 - D8 Strap: see Note 4
SA0 SA1 SA2
CS0 BA0-BA1 A0-A12 RAS CAS CKE0 WE PCK PCK
R E G I S T E R
RS0 -> CS : SDRAMs D0-D8 RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D8 RA0-RA12 -> A0-A12: SDRAMs D0 - D8 RRAS -> RAS : SDRAMs D0 - D8 RCAS -> CAS : SDRAMs D0 - D8 RCKE0 -> CKE: SDRAMs D0 - D8 RWE -> WE : SDRAMs D0 - D8 CK0, CK 0 --------- PLL* * Wire per Clock Loading Table/Wiring Diagrams
Notes: 1. DQ-to-I/O wiring may be changed within a byte. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, Adress and control resistors: 22 Ohms. 4. VDDID strap connections STRAP OUT (OPEN): VDD = VDDQ 5. SDRAM placement alternates between the back and front of the DIMM.
RESET
Figure 1
Block Diagram One Rank 16 MB x 72 DDR SDRAM DIMM Modules HYS72D16000GR-[7/8]-A using x8 organized SDRAMs on RAW Card Version A
Data Sheet
11
Rev. 1.04, 2004-01 10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A Registered DDR SDRAM Modules
Pin Configuration
VSS RS0B RS0A DQS0
DQS DQ0 DQ1 DQ2 DQ3 I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS D0 DM
DM0/DQS9
DQ4 DQ5 DQ6 DQ7 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS D9 DM
DQS1
CS D1 DM DQ8 DQ9 DQ10 DQ11
DM1/DQS10
DQ12 DQ13 DQ14 DQ15 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS D10 DM
DQS2
CS D2 DM DQ16 DQ17 DQ18 DQ19
DM2/DQS11
CS D11 DM DQ20 DQ21 DQ22 DQ23
DQS3
DM3/DQS12
CS D3 DM DQ28 DQ29 DQ30 DQ31 CS D12 DM DQ24 DQ25 DQ26 DQ27
DQS4
DQ32 DQ33 DQ34 DQ35 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS DQ56 DQ57 DQ58 DQ59 I/O 0 I/O 1 I/O 2 I/O 3 DQS CB0 CB1 CB2 CB3 CS0 BA0-BA1 A0-A11,A12 RAS CAS CKE0 WE PCK PCK I/O 0 I/O 1 I/O 2 I/O 3 CS D4 DM
DM4/DQS13
DQ36 DQ37 DQ38 DQ39
CS D13
DM
V DDSPD
EEPROM
VDD, VDDQ VREF V SS
D0 - D17 D0 - D17 D0 - D17 Strap: see Note 4
DQS5
CS D5 DM DQ40 DQ41 DQ42 DQ43
DM5/DQS14
DQ44 DQ45 DQ46 DQ47
CS D14
DM
V DDID
DQS6
DQ48 DQ49 DQ50 DQ51
CS D6
DM
DM6/DQS15
DQ52 DQ53 DQ54 DQ55
Serial PD DM SCL A0 A1 A2 SDA
CS DQS I/O 0 I/O 1 D15 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS D16
SA0 SA1 SA2
DQS7
CS D7 DM
DM7/DQS16
DQ60 DQ61 DQ62 DQ63 DM
DM
Notes: 1. DQ-to-I/O wiring may be changed within a byte. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, Adress and control resistors: 22 Ohms. 4. VDDID strap connections STRAP OUT (OPEN): VDD = VDDQ 5. SDRAM placement alternates between the back and front of the DIMM.
DQS8
CS D8
DM8/DQS17
CB4 CB5 CB6 CB7
CS D17
DM
R E G I S T E R
RS 0 -> CS : SDRAMs D0-D17
RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D17 RA0-RA11,RA12 -> A0-A11,A12: SDRAMs D0 - D17 RRAS -> RAS : SDRAMs D0 - D17 RCAS -> CAS : SDRAMs D0 - D17 RCKE0A -> CKE: SDRAMs D0 - D8 RCKEB -> CKE: SDRAMs D9 - D17 CK0, CK 0 --------- PLL* RWE -> WE : SDRAMs D0 - D17 * Wire per Clock Loading Table/Wiring Diagrams RESET
Figure 2
Block Diagram One Rank 32 MB x 72 DDR SDRAM DIMM Modules HYS72D32001GR-[7/8]-A using x4 organized SDRAMs on RAW Card Version B 12 Rev. 1.04, 2004-01 10282003-ROLI-0GQ8
Data Sheet
HYS72D[16000/32001]GR-[7/8]-A Registered DDR SDRAM Modules
Electrical Characteristics
3
3.1
Table 6 Parameter
Electrical Characteristics
Operating Conditions
Absolute Maximum Ratings Symbol min. Values typ. - - - - - - 1 50 max. -0.5 -1 -1 -1 0 -55 - - Unit Note/ Test Condition V V V V C C W mA - - - - - - - -
Voltage on I/O pins relative to VSS Voltage on inputs relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating temperature (ambient) Storage temperature (plastic) Power dissipation (per SDRAM component) Short circuit output current
VIN, VOUT VIN VDD VDDQ TA TSTG PD IOUT
VDDQ +
0.5 +3.6 +3.6 +3.6 +70 +150 - -
Attention: Permanent damage to the device may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only, and functional operation should be restricted to recommended operation conditions. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit.
Data Sheet
13
Rev. 1.04, 2004-01 10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A Registered DDR SDRAM Modules
Electrical Characteristics
Table 7 Parameter
Electrical Characteristics and DC Operating Conditions Symbol Min. 2.3 2.3 0 Values Typ. 2.5 2.5 Max. 2.7 2.7 0 V V V
2)
Unit Note/Test Condition 1)
VDD Output Supply Voltage VDDQ Supply Voltage, I/O Supply VSS, Voltage VSSQ Input Reference Voltage VREF I/O Termination Voltage VTT
Device Supply Voltage (System) Input High (Logic1) Voltage VIH(DC) Input Low (Logic0) Voltage VIL(DC) Input Voltage Level, CK and CK Inputs Input Differential Voltage, CK and CK Inputs VI-Matching Pull-up Current to Pull-down Current Input Leakage Current
--
3) 4)
0.49 x VDDQ 0.5 x VDDQ 0.51 x VDDQ V
VREF - 0.04 VREF + 0.15
-0.3 -0.3 0.36 0.71
VREF + 0.04 V VDDQ + 0.3 V VREF - 0.15 V VDDQ + 0.3 V VDDQ + 0.6
1.4 V --
7) 7) 7)
VIN(DC) VID(DC)
VIRatio
7)5)
6)
II
-2
2
A
Any input 0 V VIN VDD; All other pins not under test = 0 V 7)8) DQs are disabled; 0 V VOUT VDDQ 7)
Output Leakage Current Output High Current, Normal Strength Driver Output Low Current, Normal Strength Driver
1) 0 C TA 70 C
IOZ IOH IOL
-5 -- 16.2
5 -16.2 --
A mA mA
VOUT = 1.95 V 7) VOUT = 0.35 V 7)
2) Under all conditions, VDDQ must be less than or equal to VDD. 3) Peak to peak AC noise on VREF may not exceed 2% VREF (DC). VREF is also expected to track noise variations in VDDQ. 4) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 5) VID is the magnitude of the difference between the input level on CK and the input level on CK. 6) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. 7) Inputs are not recognized as valid until VREF stabilizes. 8) Values are shown per component
Data Sheet
14
Rev. 1.04, 2004-01 10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A Registered DDR SDRAM Modules
Electrical Characteristics
Table 8 Parameter
IDD Conditions
Symbol
Operating Current 0 one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. Operating Current 1 one bank; active/read/precharge; Burst Length = 4; see component data sheet. Precharge Power-Down Standby Current all banks idle; power-down mode; CKE VIL,MAX Precharge Floating Standby Current CS VIH,,MIN, all banks idle; CKE VIH,MIN; address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM. Precharge Quiet Standby Current CS VIHMIN, all banks idle; CKE VIH,MIN; VIN = VREF for DQ, DQS and DM; address and other control inputs stable at VIH,MIN or VIL,MAX. Active Power-Down Standby Current one bank active; power-down mode; CKE VILMAX; VIN = VREF for DQ, DQS and DM. Active Standby Current one bank active; CS VIH,MIN; CKE VIH,MIN; tRC = tRAS,MAX; DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. Operating Current Read one bank active; Burst Length = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA Operating Current Write one bank active; Burst Length = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B Auto-Refresh Current tRC = tRFCMIN, burst refresh Self-Refresh Current CKE 0.2 V; external clock on Operating Current 7 four bank interleaving with Burst Length = 4; see component data sheet.
IDD0
IDD1 IDD2P IDD2F
IDD2Q
IDD3P IDD3N
IDD4R
IDD4W
IDD5 IDD6 IDD7
Data Sheet
15
Rev. 1.04, 2004-01 10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A Registered DDR SDRAM Modules
Electrical Characteristics
Table 9
IDD Specification and Conditions
HYS72D16000GR-7-A HYS72D32001GR-7-A HYS72D16000GR-8-A HYS72D16000GR-8-A Unit Note 1)2)
Part Number & Organization
128MB x72 1 Rank -7 max. 810 990 45 405 405 135 405 990 990 1710 22.5 2520
256MB x72 1 Rank -7 max. 1620 1980 90 810 810 270 810 1980 1980 3420 45 5040
128MB x72 1 Rank -8 max. 765 900 40.5 315 315 135 315 810 855 1620 22.5 2430
256MB x72 1 Rank -8 max. 1530 1800 81 630 630 270 630 1620 1710 3240 45 4860 mA mA mA mA mA mA mA mA mA mA mA mA
3) 3)4) 5) 5) 5) 5) 5) 3)4) 3) 3) 5) 3)4)
Symbol
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1) Module IDD values are calculated on the basis of component IDD and can be measured differently according to DQ loading capacity. 2) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 3) The module IDDx values are calculated from the IDDx values of the component data sheet as follows: m x IDDx[component] + n x IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included in the calculations (see note 1) 5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) x IDDx[component]
Data Sheet
16
Rev. 1.04, 2004-01 10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A Registered DDR SDRAM Modules
Electrical Characteristics
3.2 3.3
Table 10 Parameter
Current Specification and Conditions AC Characteristics
AC Timing - Absolute Specifications -8/-7 Symbol Min. -8 DDR200 Max. +0.8 +0.8 0.55 0.55 12 12 12 -- -- -- -- +0.8 +0.8 1.25 +0.6 1.0 -- -- -- -- -- -- 0.60 -- Min. -0.75 -0.75 0.45 0.45 7 7.5 -- 0.5 0.5 2.2 1.75 -0.75 -0.75 0.75 -- -- -7 DDR266A Max. +0.75 +0.75 0.55 0.55 12 12 -- -- -- -- -- +0.75 +0.75 1.25 +0.5 0.75 -- -- -- -- -- -- 0.60 -- ns ns
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
Unit Note/ Test Condition 1)
DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width Clock Half Period Clock cycle time
DQ and DM input hold time DQ and DM input setup time Control and Addr. input pulse width (each input) DQ and DM input pulse width (each input) Data-out high-impedance time from CK/CK Data-out low-impedance time from CK/CK Write command to 1st DQS latching transition DQS-DQ skew (DQS and associated DQ signals) Data hold skew factor DQ/DQS output hold time
tAC tDQSCK tCH tCL tHP tCK2.5 tCK2 tCK1.5 tDH tDS tIPW tDIPW tHZ tLZ tDQSS tDQSQ tQHS tQH
-0.8 -0.8 0.45 0.45 8 10 10 0.6 0.6 2.5 2.0 -0.8 -0.8 0.75 -- --
tCK tCK
ns ns ns ns ns ns ns ns ns ns
min. (tCL, tCH)
min. (tCL, tCH)
CL = 2.5 2)3)4)5) CL = 2.0 2)3)4)5) CL = 1.5 2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5)6)
2)3)4)5)6)
2)3)4)5)7)
2)3)4)5)7)
tCK
ns ns ns
2)3)4)5)
2)3)4)5)
2)3)4)5) 2)3)4)5)
tHP - tQHS
0.35 0.2 0.2 2 0 0.40 0.25
tHP - tQHS
0.35 0.2 0.2 2 0 0.40 0.25
DQS input low (high) pulse width (write tDQSL,H cycle) DQS falling edge to CK setup time (write cycle) DQS falling edge hold time from CK (write cycle) Write preamble setup time Write postamble Write preamble
tCK tCK tCK tCK
ns
2)3)4)5)
tDSS tDSH
2)3)4)5)
2)3)4)5)
Mode register set command cycle time tMRD
2)3)4)5) 2)3)4)5)8) 2)3)4)5)9) 2)3)4)5)
tWPRES tWPST tWPRE
tCK tCK
Data Sheet
17
Rev. 1.04, 2004-01 10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A Registered DDR SDRAM Modules
Electrical Characteristics Table 10 Parameter AC Timing - Absolute Specifications -8/-7 Symbol Min. Address and control input setup time -8 DDR200 Max. -- -- -- -- 1.1 1.1 -- 0.60 120E+3 -- -- -- -- -- -- -- Min. 0.9 1.0 0.9 1.0 0.9 NA NA 0.40 45 65 75 20 20 20 15 15 0.60 -- -- -- -- -- -- -- -7 DDR266A Max. -- -- -- -- 1.1 ns ns ns ns fast slew rate
3)4)5)6)10)
Unit Note/ Test Condition 1)
tIS
1.1 1.1
slow slew rate
3)4)5)6)10)
Address and control input hold time
tIH
1.1 1.1
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10)
tRPRE tRPRE1.5 Read preamble setup time tRPRES Read postamble tRPST Active to Precharge command tRAS Active to Active/Auto-refresh command tRC
Read preamble period Auto-refresh to Active/Auto-refresh command period Active to Read or Write delay Precharge command period Active to Autoprecharge delay Active bank A to Active bank B command Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay
0.9 0.9 1.5 0.40 50 70 80 20 20 20 15 15
tCK tCK
ns
CL > 1.5 2)3)4)5) CL = 1.5 2)3)4)5)11)
2)3)4)5)12) 2)3)4)5) 2)3)4)5) 2)3)4)5)
tCK
ns ns ns ns ns ns ns
120E+3 ns
tRFC tRCD tRP tRAP tRRD tWR tDAL
2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
2)3)4)5) 2)3)4)5)13)
(twr/tCK) + (trp/tCK) 1 2 80 200 -- -- -- -- -- 7.8 1 -- 75 200 -- -- -- -- -- 7.8
tCK tCK tCK
ns
tWTR tWTR1.5 Exit self-refresh to non-read command tXSNR Exit self-refresh to read command tXSRD Average Periodic Refresh Interval tREFI
CL > 1.5 2)3)4)5) CL = 1.5 2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5)14)
tCK
s
1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V 2) Input slew rate 1 V/ns for DDR266, and = 1 V/ns for DDR200 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) These parameters guarantee device timing, but they are not necessarily tested on each device. 7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
Data Sheet
18
Rev. 1.04, 2004-01 10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A Registered DDR SDRAM Modules
Electrical Characteristics
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 10) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured between VOH(ac) and VOL(ac). 11) CAS Latency 1.5 operation is supported on DDR200 devices only 12) tRPRES is defined for CL = 1.5 operation only 13) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 14) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
19
Rev. 1.04, 2004-01 10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A Registered DDR SDRAM Modules
SPD Contents
4
Table 11 Byte#
SPD Contents
SPD Codes Description 128MB x72 1rank -7 HEX. 128 256 DDR-SDRAM 12 10/11 1 x72 0 SSTL_2.5 0.75 ns/0.8 ns ECC Self-Refresh 15.6 ms x8/x4 na 80 08 07 0C 0A 01 48 00 04 70 75 02 80 08 08 01 128MB x72 1rank -8 HEX. 80 08 07 0C 0A 01 48 00 04 80 80 02 80 08 08 01 256MB x72 1rank -7 HEX. 80 08 07 0C 0B 01 48 00 04 70 75 02 80 04 04 01 256MB x72 1rank -8 HEX. 80 08 07 0C 0B 01 48 00 04 80 80 02 80 04 04 01
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Number of SPD Bytes Total Bytes in Serial PD Memory Type Number of Row Addresses Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont'd) Module Interface Levels Access Time from Clock at CL = 2.5 DIMM config Refresh Rate/Type SDRAM Width, Primary Error Checking SDRAM Data Witdh
SDRAM Cycle Time at CL = 2.5 7 ns/8 ns
Minimum Clock Delay for Back- tCCD = 1 CLK to-Back Random Column Address Burst Length Supported Number of SDRAM Banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General Min. Clock Cycle Time at CAS Latency = 2 Access Time from Clock for CL = 2 Minimum Clock Cycle Time for CL = 1.5 Access Time from Clock at CL = 1.5 2, 4 & 8 4 CAS latency = 2 & 2.5 CS latency = 0 Write latency = 1 registered Concurrent Auto Precharge 7.5 ns/10 ns 0.75 ns/0.8 ns not supported not supported
16 17 18 19 20 21 22 23 24 25 26
0E 04 0C 01 02 26 C0 75 75 00 00
0E 04 0C 01 02 26 C0 A0 80 00 00
0E 04 0C 01 02 26 C0 75 75 00 00
0E 04 0C 01 02 26 C0 A0 80 00 00
Data Sheet
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Rev. 1.04, 2004-01 10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A Registered DDR SDRAM Modules
SPD Contents Table 11 Byte# SPD Codes (cont'd) Description 128MB x72 1rank -7 HEX. 27 28 29 30 31 32 33 34 35 36 to 40 41 42 43 44 45 46 to 61 62 63 64 65 to 71 72 73 to 90 91 to 92 93 to 94 95 to 98 99 to 127 Minimum Row Precharge Time Minimum Row Act. to Row Act. Delay tRRD 20 ns 15 ns 50 3C 50 2D 20 90 90 50 50 00 41 4B 0C 32 75 00 00 A7 C1 - - - - - - - 128MB x72 1rank -8 HEX. 50 3C 50 32 20 B0 B0 60 60 00 46 50 0C 3C A0 00 00 9C C1 - - - - - - - 256MB x72 1rank -7 HEX. 50 3C 50 2D 40 90 90 50 50 00 41 4B 0C 32 75 00 00 C0 C1 - - - - - - - 256MB x72 1rank -8 HEX. 50 3C 50 32 40 B0 B0 60 60 00 46 50 0C 3C A0 00 00 B5 C1 - - - - - - -
Minimum RAS to CAS Delay tRCD 20 ns Minimum RAS Pulse Width tRAS 45 ns/50 ns Module Bank Density (per Bank) 128 MByte/256 Mbyte Addr. and Command Setup Time 0.9 ns/1.1 ns Addr. and Command Hold Time 0.9 ns/1.1 ns Data Input Setup Time Data Input Hold Time Superset Information Minimum Core Cycle Time tRC 0.5 ns/0.6 ns 0.5 ns/0.6 ns - 65 ns/70 ns
Min. Auto Refresh Cmd Cycle 75 ns/80 ns Time tFRC Maximum Clock Cycle Time tCK 12 ns Max. DQS-DQ Skew tDQSQ X-Factor tQHS Superset Information SPD Revision Checksum for Bytes 0 - 62 Manufactures Module Assembly Location Module Part Number Module Revision Code Module Manufacturing Date Module Serial Number - 0.5 ns/0.6 ns 0.75 ns/1.0 ns - Revision 0.0 - - - - - - - - -
Manufactures JEDEC ID Codes -
Infineon Infineon Infineon Infineon
128 to 255 open for Customer use
Data Sheet
21
Rev. 1.04, 2004-01 10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A Registered DDR SDRAM Modules
Package Outlines
5
Package Outlines
Module Package DDR Registered DIMM Modules Raw Card A, 128 MB Module (one physical bank, 9 components)
Front View
133.35 + 0.15
4.0 max.
43.18 + 0.13
4.0
Register
2.3 typ.
PLL 52
Register 53 49.53 6.62 92
pin 1 64.77
2.3 typ.
1.27 + 0.1
Backside View
pin 93 17.80 10.0 144 145 184
2.5D
3 Detail of Contacts A 0.20 + 0.15 2.5 + 0.20 Detail of Contacts B 6.35 0.9R 3.8 typ. 1.8 2.175
3
1+ 0.05
1.27
L-DIM-184-10, Raw Card A, one bank
Figure 3
Package Outlines Raw Card A
Data Sheet
22
Rev. 1.04, 2004-01 10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A Registered DDR SDRAM Modules
Package Outlines
Module Package DDR Registered DIMM Modules Raw Card B, 256 MB Module (one physical bank, 18 components)
Front View
133.35 + 0.15
4.0 max.
43.43 + 0.13
4.0
Register
2.3 typ.
PLL 52
Register 53 49.53 6.62 92
pin 1 64.77
2.3 typ.
1.27 + 0.1
Backside View
pin 93 17.80 10.0 144 145 184
2.5D
3 Detail of Contacts A 0.20 + 0.15 2.5 + 0.20 Detail of Contacts B 6.35 0.9R 3.8 typ. 1.8 2.175
3
1 + 0.05
1.27
L-DIM-184-8, Raw Card B
Figure 4
Package Outlines Raw Card B
Data Sheet
23
Rev. 1.04, 2004-01 10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A Registered DDR SDRAM Modules
Application Note
6
Application Note
Power Up and Power Management on DDR Registered DIMMs (according to JEDEC ballot JC-42.5 Item 1173) 184-pin Double Data Rate (DDR) Registered DIMMs include two new features to facilitate controlled power-up and to minimize power consumption during low power mode. One feature is externally controlled via a systemgenerated RESET signal; the second is based on module detection of the input clocks. These enhancements permit the modules to power up with SDRAM outputs in a High-Z state (eliminating risk of high current dissipations and/or dotted I/Os), and result in the powering-down of module support devices (registers and Phase-Locked Loop) when the memory is in Self-Refresh mode. The new RESET pin controls power dissipation on the module's registers and ensures that CKE and other SDRAM inputs are maintained at a valid `low' level during power-up and self refresh. When RESET is at a low level, all the register outputs are forced to a low level, and all differential register input receivers are powered down, resulting in very low register power consumption. The RESET pin, located on DIMM tab #10, is driven from the system as an asynchronous signal according to the attached details. Using this function also permits the system and DIMM clocks to be stopped during memory Self Refresh operation, while ensuring that the SDRAMs stay in Self Refresh mode. Table 12 RESET Truth Table Register Inputs RESET H H H H L CK Rising Rising L or H High Z X or Hi-Z CK Falling Falling L or H High Z X or Hi-Z Data in (D) H L X X X or Hi-Z Register Outputs Data out (Q) H L Qo Illegal input conditions L
X: Don't care, Hi-Z: High Impedance, Qo: Data latched at the previous of CK rising and CK falling As described in the table above, a low on the RESET input ensures that the Clock Enable (CKE) signal(s) are maintained low at the SDRAM pins (CKE being one of the 'Q' signals at the register output). Holding CKE low maintains a high impedance state on the SDRAM DQ, DQS and DM outputs -- where they will remain until activated by a valid `read' cycle. CKE low also maintains SDRAMs in Self Refresh mode when applicable. The DDR PLL devices automatically detect clock activity above 20 MHz. When an input clock frequency of 20 MHz or greater is detected, the PLL begins operation and initiates clock frequency lock (the minimum operating frequency at which all specifications will be met is 95 MHz). If the clock input frequency drops below 20 MHz (actual detect frequency will vary by vendor), the PLL VCO (Voltage Controlled Oscillator) is stopped, outputs are made High-Z, and the differential inputs are powered down -- resulting in a total PLL current consumption of less than 1 mA. Use of this low power PLL function makes the use of the PLL RESET (or G pin) unnecessary, and it is tied inactive on the DIMM. This application note describes the required and optional system sequences associated with the DDR Registered DIMM 'RESET' function. It is important to note that all references to CKE refer to both CKE0 and CKE1 for a 2-bank DIMM. Because RESET applies to all DIMM register devices, it is therefore not possible to uniquely control CKE to one physical DIMM bank through the use of the RESET pin. Power-Up Sequence with RESET -- Required 1. The system sets RESET at a valid low level. This is the preferred default state during power-up. This input condition forces all register outputs to a low state independent of the condition on the register inputs (data and clock), ensuring that CKE is at a stable low-level at the DDR SDRAMs.
Data Sheet
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Rev. 1.04, 2004-01 10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A Registered DDR SDRAM Modules
Application Note 2. The power supplies should be initialized according to the JEDEC-approved initialization sequence for DDR SDRAMs. 3. Stabilization of Clocks to the SDRAM The system must drive clocks to the application frequency (PLL operation is not assured until the input clock reaches 20 MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL, the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds. When a stable clock is present at the SDRAM input (driven from the PLL), the DDR SDRAM requires 200 sec prior to SDRAM operation. 4. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector). CKE must be maintained low and all other inputs should be driven to a known state. In general these commands can be determined by the system designer. One option is to apply an SDRAM `NOP' command (with CKE low), as this is the first command defined by the JEDEC initialization sequence (ideally this would be a `NOP Deselect' command). A second option is to apply low levels on all of the register inputs to be consistent with the state of the register outputs. 5. The system switches RESET to a logic `high' level. The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous, setting the RESET timing in relation to a specific clock edge is not required (during this period, register inputs must remain stable). 6. The system must maintain stable register inputs until normal register operation is attained. The registers have an activation time that allows their clock receivers, data input receivers, and output drivers sufficient time to be turned on and become stable. During this time the system must maintain the valid logic levels described in step 5. It is also a functional requirement that the registers maintain a low state at the CKE outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time (t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to accept an input signal, is specified in the register and DIMM do-umentation. 7. The system can begin the JEDEC-defined DDR SDRAM power-up sequence (according to the JEDECpproved initialization sequence). Self Refresh Entry (RESET low, clocks powered off) -- Optional Self Refresh can be used to retain data in DDR SDRAM DIMMs even if the rest of the system is powered down and the clocks are off. This mode allows the DDR SDRAMs on the DIMM to retain data without external clocking. Self Refresh mode is an ideal time to utilize the RESET pin, as this can reduce register power consumption (RESET low deactivates register CK and CK, data input receivers, and data output drivers). 1. The system applies Self Refresh entry command. (CKELow, CSLow, RAS Low, CAS Low, WE High) Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input conditions to the SDRAM are Don't Cares-- with the exception of CKE.The system sets RESET at a valid low level. This input condition forces all register outputs to a low state, independent of the condition on the registerm inputs (data and clock), and ensures that CKE, and all other control and address signals, are a stable lowlevel at the DDR SDRAMs. Since the RESET signal is asynchronous, setting the RESET timing in relation to a specific clock edge is not required. 2. The system turns off clock inputs to the DIMM. (Optional) a. In order to reduce DIMM PLL current, the clock inputs to the DIMM are turned off, resulting in High-Z clock inputs to both the SDRAMs and the registers. This must be done after the RESET deactivate time of the register (t (INACT) ). The deactivate time defines the time in which the clocks and the control and address signals must maintain valid levels after RESET low has been applied and is specified in the register and DIMM documentation. b. The system may release DIMM address and control inputs to High-Z. This can be done after the RESET deactivate time of the register. The deactivate time defines the time in which Data Sheet 25 Rev. 1.04, 2004-01 10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A Registered DDR SDRAM Modules
Application Note the clocks and the control and the address signals must maintain valid levels after RESET low has been applied. It is highly recommended that CKE continue to remain low during this operation. 3. The DIMM is in lowest power Self Refresh mode. Self Refresh Exit (RESET low, clocks powered off) -- Optional 1. Stabilization of Clocks to the SDRAM. The system must drive clocks to the application frequency (PLL operation is not assured until the input clock reaches ~ 20 MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL, the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds. 2. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector). CKE must be maintained low and all other inputs should be driven to a known state. In general these commands can be determined by the system designer. One option is to apply an SDRAM `NOP' command (with CKE low), as this is the first command defined by the JEDEC Self Refresh Exit sequence (ideally this would be a `NOP Deselect' command). A second option is to apply low levels on all of the register inputs, to be consistent with the state of the register outputs. 3. The system switches RESET to a logic `high' level. The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous, RESET timing relationship to a specific clock edge is not required (during this period, register inputs must remain stable). 4. The system must maintain stable register inputs until normal register operation is attained. The registers have an activation time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned on and become stable. During this time the system must maintain the valid logic levels described in Step 2. It is also a functional requirement that the registers maintain a low state at the CKE outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time (t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to accept an input signal, is specified in the register and DIMM do-umentation. 5. System can begin the JEDEC-defined DDR SDRAM Self Refresh Exit Procedure. Self Refresh Entry (RESET low, clocks running) -- Optional Although keeping the clocks running increases power consumption from the on-DIMM PLL during self refresh, this is an alternate operating mode for these DIMMs. 1. System enters Self Refresh entry command. (CKE Low, CS Low, RAS Low, CAS Low, WE High) Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input conditions to the SDRAM are Don't Cares -- with the exception of CKE. 2. The system sets RESET at a valid low level. This input condition forces all register outputs to a low state, independent of the condition on the data and clock register inputs, and ensures that CKE is a stable low-level at the DDR SDRAMs. 3. The system may release DIMM address and control inputs to High-Z. This can be done after the RESET deactivate time of the register (t (INACT) ). The deactivate time describes the time in which the clocks and the control and the address signals must maintain valid levels after RESET low has been applied. It is highly recommended that CKE continue to remain low during the operation. 4. The DIMM is in a low power, Self Refresh mode. Self Refresh Exit (RESET low, clocks running) -- Optional 1. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector). CKE must be maintained low and all other inputs should be driven to a known state. In general these commands can be determined by the system designer. One option is to apply an SDRAM `NOP' command (with CKE low), as this is the first command defined by the Self Refresh Exit sequence (ideally this would be Data Sheet 26 Rev. 1.04, 2004-01 10282003-ROLI-0GQ8
HYS72D[16000/32001]GR-[7/8]-A Registered DDR SDRAM Modules
Application Note a `NOP Deselect' command). A second option is to apply low levels on all of the register inputs to be consistent with the state of the register outputs. 2. The system switches RESET to a logic 'high' level. The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous, it does not need to be tied to a particular clock edge (during this period, register inputs must continue to remain stable). 3. The system must maintain stable register inputs until normal register operation is attained. The registers have an activation time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned on and become stable. During this time the system must maintain the valid logic levels described in Step 1. It is also a functional requirement that the registers maintain a low state at the CKE outputs in order to guarantee that the DDR SDRAMs continue to receive a low level on CKE. This activation time, from asynchronous switching of RESET from low to high, until the registers are stable and ready to accept an input signal, is t (ACT ) as specified in the register and DIMM documentation. 4. The system can begin JEDEC defined DDR SDRAM Self Refresh Exit Procedure. Self Refresh Entry/Exit (RESET high, clocks running) -- Optional As this sequence does not involve the use of the RESET function, the JEDEC standard SDRAM specification explains in detail the method for entering and exiting Self Refresh for this case. Self Refresh Entry (RESET high, clocks powered off) -- Not Permissible In order to maintain a valid low level on the register output, it is required that either the clocks be running and the system drive a low level on CKE, or the clocks are powered off and RESET is asserted low according to the sequence defined in this application note. In the case where RESET remains high and the clocks are powered off, the PLL drives a High-Z clock input into the register clock input. Without the low level on RESET an unknown DIMM state will result.
Data Sheet
27
Rev. 1.04, 2004-01 10282003-ROLI-0GQ8
http://www.infineon.com
Published by Infineon Technologies AG

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